Silicon Electrical Engineer - RTL Design 5

  • Experis
  • Mountain View, California
  • Full Time

Title: Senior Hardware Design Engineer SoC Integration
Location: Mountain View, CA
Experience Level: Senior (10+ years)

About the Role
We are seeking a highly experienced Senior Hardware Design Engineer SoC Integration to join our cutting-edge silicon design team focused on developing next-generation cloud and AI products. This role offers a dynamic and engaging environment where you will contribute to SoC integration, IP development, and design flow optimization.

Key Responsibilities

  • Lead and support SoC integration efforts, contributing to 50% of daily tasks.
  • Develop and implement RTL designs using SystemVerilog for digital IPs.
  • Perform CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and lint checks to ensure design quality.
  • Write and maintain scripts to support design automation and flow improvements.
  • Collaborate with cross-functional teams to integrate IPs and subsystems.
  • Debug and resolve design issues, contributing to robust and reliable silicon tapeouts.
  • Analyze performance, power, and area trade-offs for digital designs.
  • Support verification teams and contribute to testbench development.
  • Participate in front-end synthesis and timing analysis.
Required Qualifications
  • 10+ years of experience in digital hardware design and SoC development.
  • Proven track record of contributing to successful SoC tapeouts.
  • 5+ years of experience with AXI protocol integration.
  • 7+ years of experience with CDC and RDC design practices.
  • 5+ years of experience developing small IP blocks.
  • Proficiency in SystemVerilog , RTL design, and scripting languages (Python, Perl).
  • Strong understanding of AXI/APB protocols , subsystem design, and SoC integration.
  • Experience with simulation, debugging, and design verification tools.
  • Familiarity with DFT and scan methodologies.
  • Bachelors degree in Electrical Engineering, Computer Engineering, or related field (Masters preferred).
Preferred Qualifications
  • Experience with ARM core-side protocols and verification testbenches.
  • Background in floating-point arithmetic implementation.
  • Prior experience working in large enterprise environments on complex tapeouts.
Why Join Us?
  • Work on state-of-the-art silicon chips powering the future of cloud and AI.
  • Enjoy a diverse and engaging workload no two days are the same.
  • Be part of a collaborative and innovative team at the forefront of technology.

If this is a role that interests you and youd like to learn more, click apply now and a recruiter will be in touch with you to discuss this great opportunity. We look forward to speaking with you!

About ManpowerGroup, Parent Company of: Manpower, Experis, Talent Solutions, and Jefferson Wells

ManpowerGroup (NYSE: MAN), the leading global workforce solutions company, helps organizations transform in a fast-changing world of work by sourcing, assessing, developing, and managing the talent that enables them to win. We develop innovative solutions for hundreds of thousands of organizations every year, providing them with skilled talent while finding meaningful, sustainable employment for millions of people across a wide range of industries and skills. Our expert family of brands Manpower, Experis, Talent Solutions, and Jefferson Wells creates substantial value for candidates and clients across more than 75 countries and territories and has done so for over 70 years. We are recognized consistently for our diversity - as a best place to work for Women, Inclusion, Equality and Disability and in 2022 ManpowerGroup was named one of the World's Most Ethical Companies for the 13th year - all confirming our position as the brand of choice for in-demand talent.

Job ID: 481616093
Originally Posted on: 6/17/2025

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