Physical Design Engineer
Job Role:
Physical Designer
Location:
Chicago, IL
(Day 1 Onsite)
Duration:
6+ Months
ROLE DESCRIPTION:
Experience Required:
6 - 8 Years
Physical Design- Backend Engineer
Should have in depth experience in Synthesis, Floor-planning, Power routing, place and route, CTS, timing closure, DRC and LVS
Should have worked on the latest technology nodes 22GFT
Must have experience in Static timing analysis
Must have experience in Physical verification and appropriate fixes
Should have worked on block level and top-level design experience is plus
Strong problem-solving skills and communication skills
Educational Qualification:
BE/ME or BTech /MTech (BS/MS)
ESSENTIAL SKILLS:
Synthesis, Floor-planning, Power routing, place and route, CTS, timing closure, DRC and LVSAnalog/RF layout/mask designers with experience in GF 22FDX, 22nm SOI, layout, physical designer, mask designer, Cadence Virtuoso, Pegasus, Calibre, DRC, LVS, SOI CMOS, BiCMOS.
Employers have access to artificial intelligence language tools (AI) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job
Dice Id:
10501519
Position Id:
8679473
Job Role:
Physical Designer
Location:
Chicago, IL
(Day 1 Onsite)
Duration:
6+ Months
ROLE DESCRIPTION:
Experience Required:
6 - 8 Years
Physical Design- Backend Engineer
Should have in depth experience in Synthesis, Floor-planning, Power routing, place and route, CTS, timing closure, DRC and LVS
Should have worked on the latest technology nodes 22GFT
Must have experience in Static timing analysis
Must have experience in Physical verification and appropriate fixes
Should have worked on block level and top-level design experience is plus
Strong problem-solving skills and communication skills
Educational Qualification:
BE/ME or BTech /MTech (BS/MS)
ESSENTIAL SKILLS:
Synthesis, Floor-planning, Power routing, place and route, CTS, timing closure, DRC and LVSAnalog/RF layout/mask designers with experience in GF 22FDX, 22nm SOI, layout, physical designer, mask designer, Cadence Virtuoso, Pegasus, Calibre, DRC, LVS, SOI CMOS, BiCMOS.
Employers have access to artificial intelligence language tools (AI) that help generate and enhance job descriptions and AI may have been used to create this description. The position description has been reviewed for accuracy and Dice believes it to correctly reflect the job opportunity.
Report this job
Dice Id:
10501519
Position Id:
8679473
Job ID: 483025956
Originally Posted on: 6/27/2025
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