Senior RTL Design Engineer

Join to apply for the Senior RTL Design Engineer role at Prodapt

Join to apply for the Senior RTL Design Engineer role at Prodapt

Overview

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises.

Overview

Prodapt is a global technology company and the largest specialized player in the Connectedness industry. As an AI-first strategic partner, Prodapt provides consulting, business transformation, and managed services to top telecom and tech enterprises. Prodapt ASIC Services is a leading provider of SoC ASIC/FPGA and Embedded Software services . We offer turnkey solutions, Offshore Design Centers (ODCs), and staff augmentation across key areas like RTL Design, UVM Verification, Emulation, FPGA Validation, DFT, RTL-to-GDSII, Physical Design, Mask Layout, and Silicon Bring-up. Our Embedded services include firmware, device drivers, RTOS porting, and board bring-up . A Great Place To WorkCertified company, Prodapt employs over 6,000 technology and domain experts in 30+ countries. Prodapt is part of the 130-year-old business conglomerate The Jhaver Group, which employs over 32,000 people across 80+ locations globally.

Prodapt is looking for a Senior RTL Design Engineer who has recent experience working on complex SoCs using RTL Coding from Scratch, Microarchitecture, CDC, LINT

Location: El Segundo, CA/Mountain View, CA

Responsibilities

What you'll be doing:

• Proficiency in RTL coding, synthesis, and/or SoC integration
• Familiarity with digital design microarchitecture

Knowledge of Verilog and SystemVerilog coding

Requirements

What you'll have:

• Bachelor's degree in Electrical Engineering, Computer Science, or equivalent with Minimum 10+ years of experience as a Digital Design Engineer and experience in RTL coding, synthesis, and/or SoC integration
• Familiarity with digital design microarchitecture
• Familiarity with UPF-based simulation flow
• Experience with System Verilog, CDC, Lint and Spyglass
• Proficiency in Tcl and Python (or similar) scripting
• Knowledge of SoC integration and ASIC architecture

Seniority level

• Seniority level Not Applicable

Employment type

• Employment type Full-time

Job function

• Job function Engineering and Information Technology
• Industries Technology, Information and Internet

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