Engineering**
**Design Engineer 3** Harrisburg, PA Posted: 7/14/2025
Job Description
Job ID#:
212144
Job Category:
Engineering
Position Type:
Associate - W2
Duration:
52
Shift:
1
**PDS Defense, Inc. is seeking a Remote Design Engineer 3. Job ID#212144**
Pay Rate: $88- $93/hr
**Job Description:**
Seeking a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.
Responsibilities:
Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts
Adhering to ASIC development process.
Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies.
Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.
Basic Qualifications
Bachelor's degree in Electrical or Computer Engineering with 8+ years' experience.
Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience
U.S. Citizenship is required
Experience in full product life cycle of ASIC Design
Experience with Cadence and/or Mentor test insertion and ATPG tools
Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG)
Experience with memory BIST and logic BIST
Experience generating test patterns and analyzing and debugging test failures
Experience working with test engineers to implement ATPG vectors on tester hardware
Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl
Effective communication and presentation skills and high proficiency in technical problem solving
Preferred Qualifications:
Master's Degree in Electrical or Computer Engineering
Expertise of using Cadence Modus DFT tools
Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
**Exclusive Bonus Opportunity!**
A limited time bonus program is currently available for this role. Speak with your recruiter today to determine eligibility before it's gone! Offer expires September 30th, 2025.
Job Requirements
Minimum Security Clearance:
No Clearance
**VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled**
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit ** or **
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
+ The California Fair Chance Act
+ Los Angeles City Fair Chance Ordinance
+ Los Angeles County Fair Chance Ordinance for Employers
+ San Francisco Fair Chance Ordinance
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
**Design Engineer 3** Harrisburg, PA Posted: 7/14/2025
Job Description
Job ID#:
212144
Job Category:
Engineering
Position Type:
Associate - W2
Duration:
52
Shift:
1
**PDS Defense, Inc. is seeking a Remote Design Engineer 3. Job ID#212144**
Pay Rate: $88- $93/hr
**Job Description:**
Seeking a DFT (Design for Test) engineer to join our highly qualified, diverse individuals as part of our ASIC design team.
Responsibilities:
Responsible for DFT (Design for Testability) aspects of ASIC Design thorough understanding of digital design concepts
Adhering to ASIC development process.
Knowledgeable in VHDL, Verilog or System Verilog RTL coding and highly proficient in DFT methodologies.
Responsible for operating in a team environment and collaborating across the different teams as required to accomplish the goals.
Basic Qualifications
Bachelor's degree in Electrical or Computer Engineering with 8+ years' experience.
Bachelor's degree with 8 years of experience, a Master's degree with 6 years of experience
U.S. Citizenship is required
Experience in full product life cycle of ASIC Design
Experience with Cadence and/or Mentor test insertion and ATPG tools
Experience with hierarchical scan testing, IEEE-1500 and/or IEEE-1687, test compression, JTAG IEEE-1149.1 and IEEE-1149.6 (AC JTAG)
Experience with memory BIST and logic BIST
Experience generating test patterns and analyzing and debugging test failures
Experience working with test engineers to implement ATPG vectors on tester hardware
Proficiency in HDL (VHDL/Verilog/System Verilog) and scripting languages such as Tcl, Python or Perl
Effective communication and presentation skills and high proficiency in technical problem solving
Preferred Qualifications:
Master's Degree in Electrical or Computer Engineering
Expertise of using Cadence Modus DFT tools
Knowledge of Synthesis, P&R and Static Timing Analysis would be a plus
Benefits offered to vary by the contract. Depending on your temporary assignment, benefits may include direct deposit, free career counseling services, 401(k), select paid holidays, short-term disability insurance, skills training, employee referral bonus, affordable medical coverage plan, and DailyPay (in some locations). For a full description of benefits available to you, be sure to talk with your recruiter.
**Exclusive Bonus Opportunity!**
A limited time bonus program is currently available for this role. Speak with your recruiter today to determine eligibility before it's gone! Offer expires September 30th, 2025.
Job Requirements
Minimum Security Clearance:
No Clearance
**VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled**
To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit ** or **
The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable:
+ The California Fair Chance Act
+ Los Angeles City Fair Chance Ordinance
+ Los Angeles County Fair Chance Ordinance for Employers
+ San Francisco Fair Chance Ordinance
VEVRAA Federal Contractor / Request Priority Protected Veteran Referrals / Equal Opportunity Employer / Veterans / Disabled
Job ID: 485228180
Originally Posted on: 7/15/2025
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