Memory Design Engineer

• Work on transistor level design of analog and mixed signal circuits in memory (SRAM/DRAM) for display chip or image sensor.
• Conducted full-chip, block-level, and transistor-level simulations using HSPICE/Spectre to validate functionality.
• Perform the block level and transistor level layout design using CAD tools like Cadence Virtuoso and Calibre.
• Collaborate with verification, process, test, and application engineers to debug, characterize and optimize the performance.

Requirements: Masters degree or foreign equivalent degree in Electrical Engineering, Computer Engineering or related fields. Require advanced level courses of VLSI Design, A/D Interfaces, Computer Architecture, and Monolith Amplifier Circuits. Required skills:

• Transistor level design and layout optimization.
• CAE tools associated with Analog-mixed signal IC design and verification including transistor level simulators, power analysis, noise analysis, mixed-mode simulation, parasitic extraction.
• Circuit simulation with back annotated parasitics and corner simulations.
• Scripting Languages, e.g., PERL or Python or Tcl/Tk.
• Spice Simulators with statistical variation: HSPICE with Monte Carlo simulation variation analysis.
• Circuit design such as Virtuoso, Calibre, PrimeTime, Encounter/Innovus, Design Compiler, SPICE.
• Circuit design with focus on memory design and schematic capture and performance measurement.
• Root-cause analysis for LVS, DRC, and ERC issues.
• Knowledge of semiconductor physics.
• MOS transistors basics, and small signal analysis.

Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.