RTL/ASIC/SoC Design Engineer

Akkodis is seeking an experienced and innovative ASIC / SoC Design Engineer to contribute to the development of advanced memory subsystem controllers and interface technologies. In this role, you will work from high-level architectural specifications to define microarchitectures, implement RTL, integrate third-party IPs, and deliver PPA-optimized ASIC/SoC designs through to tape-out. Salary : $140k - $200k/annual - Salary may be negotiable based upon experience, education, geographic location, and other factors Job Type : Direct Hire, Full-Time Location : Irvine, CA (Possible Hybrid/ Remote) Responsibilities : Translate architectural specifications into block-level microarchitecture with a focus on power, performance, and area (PPA) optimization Develop synthesizable RTL in Verilog or SystemVerilog for custom controller, interface, and logic modules Integrate and validate third-party IP cores including PCIe, CXL, DDR3/4/5, NAND, and SSD-related interfaces Perform functional simulations, unit-level verification, and assertion-based checks Execute logic synthesis, static timing analysis (STA), clock domain crossing (CDC) checks, and timing closure Collaborate across hardware, firmware, validation, and physical design teams to drive full-chip integration Support bring-up and post-silicon validation of ASICs and FPGA prototypes Contribute to design reviews, documentation, and test planning Required Qualifications: BS in Electrical or Computer Engineering with 10+ years of relevant design experience, or MS with 8+ years in ASIC / SoC hardware development Demonstrated expertise in PCIe, CXL, DDR3/DDR4/DDR5, NAND flash, and SSD controller design Solid understanding of RTL design, digital logic principles, and ASIC/SoC development flows Proficient in EDA tools for synthesis, STA, and CDC analysis Experience integrating and validating commercial IP blocks in complex SoC environments Strong debugging, problem-solving, and analytical skills Excellent communication and documentation abilities Preferred Qualifications: Tape-out experience with high-performance ASICs or SoCs Familiarity with HLS tools, formal verification, or low-power design flows Experience with FPGA prototyping platforms (Xilinx, Intel/Altera) Background in memory controller or storage-class memory architecture Prior experience in CXL controller design or verification ________________________________________ For other opportunities available at Akkodis go to www.akkodis.com If you have questions about the position, please contact ... Equal Opportunity Employer/Veterans/Disabled Benefit offerings available for this direct hire position include medical, dental, vision, additional voluntary benefits, and a 401K plan. To read our Candidate Privacy Information Statement, which explains how we will use your information, please visit The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable: The California Fair Chance Act Los Angeles City Fair Chance Ordinance Los Angeles County Fair Chance Ordinance for Employers San Francisco Fair Chance Ordinance Pay Details: $140,000.00 to $200,000.00 per year Equal Opportunity Employer/Veterans/Disabled To read our Candidate Privacy Information Statement, which explains how we will use your information, please navigate to The Company will consider qualified applicants with arrest and conviction records in accordance with federal, state, and local laws and/or security clearance requirements, including, as applicable: The California Fair Chance Act Los Angeles City Fair Chance Ordinance Los Angeles County Fair Chance Ordinance for Employers San Francisco Fair Chance Ordinance