Sr. Staff Physical Design Engineer

4Ghz) APR and PV signoff for 3nm or latest technology nodes. Advanced clock tree structure, Multi-Voltage domains, FIFO interface, Partition implementation. Conducting PPA evaluation and risk assessment in the early stages of the project.

• Minimum of 10 years of hands-on experience in Physical Design. Proficiency in Python, TCL, and Make scripting. Prior experience in CPU physical implementation is a plus. Additional experience in Synthesis, Formal Equivalence Checking, Flow Automation, IR Analysis, and STA Analysis is advantageous. #LI-NL1