Timing Design Engineer

Job Summary

Summary Posted: Jan 22, 2026 Role Number: 20... Apple is where individual imaginations come together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each others ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. Its the diversity of our people and their thinking that encourages the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, youll do more than join something youll add something.

Description

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

EEO Notice

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