Senior Digital Validation Engineer

Secure Transactions and Identification (STI) works at the forefront of technology providing solutions for mobile wallet (payment, transit, access), mobile security, and UWB in consumer products ranging from wearables, smart phones to laptops.

STI Digital Validation team is responsible for ensuring the functionality, performance, and robustness of SoC devices across presilicon and postsilicon phases. We are seeking a Senior Digital Validation Engineer to work at San Diego location with deep SoC validation experience and a passion for ARM and RISCV based architectures , lowlevel software development, handson lab bringup, scalable validation automation, and standard SoC communication interfaces .

In this role, you will take technical ownership of validation efforts , lead complex systemlevel debug, and design automation solutions that enable efficient, repeatable silicon validation.

Key Responsibilities

• Own and drive blocklevel and systemlevel validation strategy , including validation scope, coverage, and test planning

• Perform deep analysis of specifications and system use cases to ensure complete functional, performance, and interface coverage

• Review validation strategies with key stakeholders, including design leads, system teams, and architects

• Implement and maintain validation test infrastructure using C and Java

• Validate interface functionality, performance, power behavior, and corner cases across operating modes

• Lead validation on presilicon platforms , such as FPGA emulation

• Execute and guide postsilicon validation campaigns , including silicon bringup, evaluation, and characterization

• Perform handson lab validation using oscilloscopes, advanced power supplies, DMMs, source meters (SMUs), waveform generators, and temperature controllers

• Design and implement automation solutions for validation workflows, including:

  • Automated test execution and sequencing

  • Instrument control and configuration

  • Data collection, analysis, and reporting

  • Regression testing across silicon revisions

• Develop automation primarily using Python , integrating lowlevel C test code with higherlevel control frameworks

• Drive complex hardware/software codebug , including rootcause analysis of interface, protocol, and timingrelated issues

• Mentor junior engineers and provide technical leadership in validation and automation best practices

Required Qualifications

• Masters degree in Computer Science, Computer Engineering, Electrical Engineering

• At least 5 years of industry related experience

• Strong professional experience in SoC digital validation

• Extensive experience with embedded C programming with either ARM or RISCV based microcontrollers.

• Proficiency in at least one objectoriented programming language (Java, C++, C#, etc.)

• Strong experience with automation and scripting , preferably Python

• Handson experience validating SoC communication interfaces such as I2C / I3C, SPI, SPMI, ISOUART (7816)

• Strong handson lab experience with electrical measurement and control equipment, including:

  • Oscilloscopes

  • Programmable power supplies

  • DMMs

  • Source meters (SMUs)

  • Waveform / signal generators

  • Temperature / thermal controllers

• Proven ability to debug complex issues across protocol, hardware, firmware, and system levels

• Strong sense of ownership, technical judgment, and attention to detail

Preferred Qualifications (Nice to Have)

• Background in design verification or close collaboration with DV teams

• Experience with postsilicon logic debug , including deep analysis of test logs

• Experience developing software hooks or firmware instrumentation for debug

• Familiarity with ARM or RISCVbased SoC architectures and system bringup

• Experience improving validation workflows through automation, regression frameworks, or lab infrastructure standardization

Why Join This Role

• Seniorlevel ownership with direct impact on silicon readiness and product quality

• Strong emphasis on handson lab work, block level and system level validation, interface validation, and automation

• Opportunity to influence validation methodology and tooling

• Exposure to the full SoC lifecycle, from presilicon through production silicon

• Close collaboration with architecture, design, systems, and validation teams

The base salary range for this position is as mentioned below per year. We also provide competitive benefits, incentive compensation, and/or equity for certain roles.
Company benefits include health. dental, and vision insurance. 401(k), and paid leave. Please note that the base salary range (OR hourly rate) is a guideline, and individual total compensation may vary based on a number of factors such as qualifications, skill level, work location, and other business and organizational needs. This base pay range is specific to California and is not applicable to other locations. A reasonable estimate of the base salary range as of the date of this posting is:

More information about NXP in the United States...

NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals.