FPGA/ASIC Design Engineer

5 yrs, Xilinx FPGA design EDA- Vivado Must have done hands on multiple complex designs arch/design/verification/Synthesis/STA Big Plus Working with Ethernet protocol (not just instantiating the IP) Is a big plus. Mentor EDA CDC/Lint/AC/RDC POSITION RESPONSIBILITIES: The FPGA/ASIC Design Engineer will be responsible for the architecture, implementation, verification/validation through Software integration test, for delivery of complex FPGAs AND/OR ASICs systems. This is a key, high impact, high visibility role in the organization to ensure robust quality and delivery of Communication products for National Security. Develop architectures for implementation of high throughput complex designs involving Cryptographic Algorithms (VHDL) with high speed protocols NVMe, PCIe/SRIOV, 10G-400G Ethernet, TCP/IP, and IP development/integration targeting ARM SOC FPGAs (Ex. Xilinx MPSOC) AND/OR ASICs. Additionally, S/He will be responsible for writing/debugging tests/sequences for End-to-End simulation on UVM framework, with System Verilog Assertions, and also writing/debugging C++ based SW driven validation on SOC evaluation boards (Xilinx MPSOC) running Linux. PREFERRED QUALIFICATIONS (DESIRED SKILLS/EXPERIENCE): High Level Synthesis (HLS) with Vivado, Embedded SW C++ (OOP) and System Verilog Assertions (SVA). Knowledge of high-speed protocols (PCIe, TCP/IP, Ethernet). PHYSICAL REQUIREMENTS (if noted by client in their req): REQUIRED EDUCATION: Bachelor of Science in Electrical Engineering or Computer Science or equivalent Master of Science in Electrical Engineering or Computer Science preferred. **Education MUST be accredited** WORK HOURS: Full-Time Monday-Friday 08:00am-05:00pm ADDITIONAL: Active secret clearance required.