Sr. ASIC Design Engineer

Responsibilities:

• Member of design team for large SOCsQualifications:

• BS/MS degree with 5+ years of relevant work experience

• Good understanding of digital design and verification practices

• Ability to write RTL based on a specification and simulate vectors to verify RTL

• Experience using System Verilog (SV) and at least one prior RTL designs

• Familiarity with PCIe, USB3, or Power Delivery

Experience:

• Demonstrate an expert knowledge of System Verilog (SV) or similar verification language
• Demonstrate an expert knowledge of Verilog for chip design and verification
• Understanding the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, first silicon bring up and debug
• Experience with high-speed serial protocols (USB3, PCIe, Ethernet, etc.)
• Experience with creating module level test benches and BFMs