Functional Safety Engineer

Must have good technical skills ABOUT THE ROLE We are seeking a technically deep Functional Safety Engineer to own hardware-level safety analysis across EV electronics platforms. You will serve as the safety authority applying ISO 26262 Part 5 requirements to high-voltage powertrain, battery management, and chassis control systems - partnering with hardware, firmware, and systems teams to embed safety into design from day one. KEY RESPONSIBILITIES FMEDA: Lead and execute FMEDA for electronic hardware elements - ASICs, SoCs, PMICs, microcontrollers, power electronics - evaluating SPFM, LFM, and PMHF against ASIL-B/C/D targets.

Fault Tree Analysis: Perform quantitative FTA at hardware and system levels; compute minimal cut sets and top-event probabilities vs. safety goals.

Dependent Failure Analysis: Conduct DFA to identify and mitigate common-cause and cascading failures; ensure freedom-from-interference across safety-critical subsystems.

Mission Profiles & FIT Rates: Define and apply custom mission profiles for California EV operating conditions; accurately compute component FIT rates using IEC TR 62380, SN 29500, or MIL-HDBK-217.

Tool Expertise: Execute safety analyses in Ansys Medini Analyze and Isograph Reliability Workbench; maintain reusable component libraries and diagnostic coverage templates.

Safety Architecture: Develop hardware safety concepts, requirements, and architecture for electronics subsystems; drive upstream/downstream traceability in JAMA or DOORS.

REQUIRED QUALIFICATIONS BS/MS in Electrical Engineering or related field

6+ years (BS) or 4+ years (MS) in functional safety

Hands-on ISO 26262 Part 5 hardware safety analysis

FTA, FMEDA, DFA - component to system level

FIT rate computation: IEC TR 62380, SN 29500, MIL-HDBK-217

Ansys Medini Analyze and/or Isograph Reliability Workbench

Custom mission profile definition and application

ASIL decomposition, safety mechanisms, diagnostic coverage

PREFERRED QUALIFICATIONS ISO 26262 FSE Certification (TUV Rheinland / TUV SUD)

ASIL-C/D HW dev: HV BMS, Inverter, or OBC systems

Familiarity with SOTIF (ISO 21448) integration

Circuit simulation: LTSpice or equivalent

IEC 61508, IEC 62443 (cybersecurity-safety overlap)

Requirements tools: JAMA Connect, IBM DOORS, Polarion

Experience with STPA (System-Theoretic Process Analysis)

Power electronics failure mode analysis background

TOOLS & TECHNOLOGIES Ansys Medini Isograph RWB JAMA Connect IBM DOORS LTSpice FTA / FMEDA / DFA SPFM / LFM / PMHF IEC TR 62380 SN 29500 ASIL-D