Sr Principal ASIC Design Engineer (NetSec)

Our Mission

At Palo Alto Networks everything starts and ends with our mission:

Being the cybersecurity partner of choice, protecting our digital way of life.
Our vision is a world where each day is safer and more secure than the one before. We are a company built on the foundation of challenging and disrupting the way things are done, and were looking for innovators who are as committed to shaping the future of cybersecurity as we are.

Who We Are

We take our mission of protecting the digital way of life seriously. We are relentless in protecting our customers and we believe that the unique ideas of every member of our team contributes to our collective success. Our values were crowdsourced by employees and are brought to life through each of us everyday - from disruptive innovation and collaboration, to execution. From showing up for each other with integrity to creating an environment where we all feel included.

As a member of our team, you will be shaping the future of cybersecurity. We work fast, value ongoing learning, and we respect each employee as a unique individual. Knowing we all have different needs, our development and personal wellbeing programs are designed to give you choice in how you are supported. This includes our FLEXBenefits wellbeing spending account with over 1,000 eligible items selected by employees, our mental and financial health resources, and our personalized learning opportunities - just to name a few!

At Palo Alto Networks, we believe in the power of collaboration and value in-person interactions. This is why our employees generally work full time from our office with flexibility offered where needed. This setup fosters casual conversations, problem-solving, and trusted relationships. Our goal is to create an environment where we all win with precision.

Your Career

Join our ASIC team and help deliver the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or subsystems from architectural definition through silicon bring-up. You will provide technical leadership, collaborate extensively with world-class verification and physical design engineers to hit aggressive performance, power, and schedule goals, and mentor less experienced team members. This role requires a deep technical background in ASIC design for networking applications and the ability to independently drive major design efforts.

Your Impact

• Define and document clear, comprehensive design and micro-architecture specifications for complex digital logic blocks and subsystems.

• Design high-quality, high-performance SystemVerilog RTL that meets aggressive area, performance, and power targets, with particular emphasis on complex datapath designs.

• Lead debug efforts across simulation, emulation, formal methods, and silicon bring-up environments.

• Partner closely with verification engineers to define test plans, debug complex scenarios, close coverage, and add design-for-debug features.

• Collaborate effectively with physical design teams, including reviewing synthesis/timing reports, rewriting RTL to close critical paths, analyzing timing, power, and area reports, and consulting on floor-planning for congestion/routability. Drive timing closure from an RTL perspective, understanding core concepts like setup/hold constraints and delay sources.

• Mentor junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC design best practices, particularly in areas like design methodology and problem-solving approach.

Your Experience

Required Qualifications

• BS in EE, CE, or CS (MSEE or equivalent military experience preferred).

• 15+ years of hands-on front-end ASIC design experience, with significant ownership of multiple complex modules or subsystems from specification through mass production silicon.

• Expert-level proficiency in SystemVerilog RTL design.

• Deep and demonstrable strength in digital logic design fundamentals, including state machines, synchronous and asynchronous FIFO design, flow control mechanisms (e.g., ready/valid, credits, backpressure), and the understanding and avoidance of head-of-line blocking and deadlock situations in complex datapaths.

• Expertise in defining micro-architecture from high-level requirements for large and intricate digital blocks.

• Advanced debugging skills across various verification platforms and silicon.

• Strong command of timing, power, and area analysis, with proven ability to analyze reports, identify critical paths, and drive RTL changes to meet targets effectively.

• Proficiency in scripting (Python, C/C++, Perl, bash, or tcsh) for automation and analysis.

• Excellent technical leadership, collaboration, and written/verbal communication skills, including the ability to clearly explain complex design concepts and methodologies.

• Strong networking or cybersecurity domain knowledge.

• Extensive experience with relevant protocols/technologies (e.g., PCIe, Ethernet IEEE 802.3, search-algorithm accelerators, ARM AMBA buses like AXI/AHB/APB, cryptographic algorithms).

• Hands-on silicon validation and lab bring-up experience .

Preferred / Nice-to-Have

• Formal verification ownership and expertise.

• Experience with innovation or piloting new design or verification flows (e.g., AI-driven techniques).

The Team

We are the global cybersecurity leader, known for always challenging the security status quo. Our mission is to protect our way of life in the digital age by preventing successful cyberattacks. This has given us the privilege of safely enabling tens of thousands of organizations and their customers. Our pioneering Security Operating Platform emboldens their digital transformation with continuous innovation that seizes the latest breakthroughs in security, automation, and analytics. By delivering a true platform and empowering a growing ecosystem of change-makers like us, we provide highly effective and innovative cybersecurity across clouds, networks, and mobile devices.

Our Security Operating Platform is built for automation. It is easy to operate, with capabilities that work together, so customers can prevent successful cyberattacks. They can use analytics to automate routine tasks, so they can focus on what matters. We are known for continuously delivering innovations; and with Application Framework, we extend that to an open ecosystem of developers that benefit from our customers existing investment in data, sensors, and enforcement points.

Compensation Disclosure

The compensation offered for this position will depend on qualifications, experience, and work location. For candidates who receive an offer at the posted level, the starting base salary (for non-sales roles) or base salary + commission target (for sales/commissioned roles) is expected to be between $220000 - $252000/YR. The offered compensation may also include restricted stock units and a bonus. A description of our employee benefits may be found here .

Our Commitment

Were problem solvers that take risks and challenge cybersecuritys status quo. Its simple: we cant accomplish our mission without diverse teams innovating, together.

We are committed to providing reasonable accommodations for all qualified individuals with a disability. If you require assistance or accommodation due to a disability or special need, please contact us at [email protected] .

Palo Alto Networks is an equal opportunity employer. We celebrate diversity in our workplace, and all qualified applicants will receive consideration for employment without regard to age, ancestry, color, family or medical care leave, gender identity or expression, genetic information, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran status, race, religion, sex (including pregnancy), sexual orientation, or other legally protected characteristics.

All your information will be kept confidential according to EEO guidelines.