Senior Design Engineer (ASIC/RTL Design)

We have an open position for a Senior ASIC/RTL Design Engineer with one of our esteemed clients. Please connect with us to know more about this opportunity. Job Title: Senior ASIC/RTL Design Engineer Work Location: Santa Clara, CA Top skills: Good understanding of System Verilog, analyzing existing designs and making modifications, able to understand tools used by ASIC engineers like Lint, CDC, STA, etc. - scripting is nice to have Experience Required: 5-6+ years' experience required Must have proven track record of ASIC design on several production tape-outs. Experience in Designing RTL block for an SOC. Experience in integrating ASIC IP into an SOC. Experience with synthesis, static timing analysis & optimizations. KEY RESPONSIBILITIES: Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements. Collaborate with architecture and hardware teams to understand the requirements. Work with verification and physical design teams to achieve high quality design and successful tape out. Design and implement logic functions that enable efficient test and debug. Participate in silicon bring-up for features owned. Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features. Implement automation to increase design team efficiency.