Principal Design Engineer Manager - AI Network Silicon

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsofts expanding Cloud Infrastructure and responsible for powering Microsofts Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.

As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, the AI Silicon Engineering (AISiE) team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a **Principal Design Engineer Manager - AI Network Silicon** to join the team.

Microsofts mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond.

**Responsibilities**

+ Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features.

+ Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP.

+ Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent.

+ Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design.

+ Provide technical leadership through mentorship and teamwork.

+ Embody our culture ( and values. (

**Qualifications**

**Minimum Qualifications:**

+ Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience

+ OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience

+ OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience

+ OR Equivalent Experience.

+ 3+ years expertise in digital logic design including microarchitecture specification development, RTL coding in Verilog/System Verilog, design verification collaboration, and CDC/Lint closure.

+ 3+ years of experience in synthesis, timing constraints, power / performance / area (PPA) trade-offs and post-silicon debug.

**Other Requirements:**

Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include, but are not limited to, the following specialized security screenings:

+ Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud background check upon hire/transfer and every two years thereafter.

**Preferred** **Qualifications:**

+ 9+ years of related technical engineering experience

+ OR Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience or internship experience

+ OR Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience or internship experience

+ OR Doctorate degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience.

+ 15+ years of experience in logic design delivering complex solutions

+ Successful development of High-Speed NIC, Networking Interface and Protocol Processing pipeline for multiple SOCs

+ Understanding of various Network Topology and System level challenges to design high performance Scale up and Scale Out Networks

+ Work experience of >100G Ethernet based Interface Architecture and Design

+ Understanding of L1 to L4 layers of Network Protocol stack

+ Good understanding of End-to-End Transport Protocol Architecture challenges for large scale Network (including Congestion in network, Flow Control, Topologies, Load Balancing, Traffic pattern, Uniform Latency)

+ Experience leading logic design teams

+ Multiple successfulASIC tape outs in deep sub-micron technologies

+ Experience with scripting languages such as Python or Perl

+ Experience debugging designs as well as simulation environment

+ Knowledge of verification principles, testbenches, UVM, and coverage

+ Experience working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs

+ Working knowledge of writing assertions, coverage and formal verification

Silicon Engineering M5 - The typical base pay range for this role across the U.S. is USD $139,900 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here: US corporate pay information | Microsoft Careers (

Microsoft will accept applications for the role until July 27th, 2025.

\#SCHIE \#azurehwjobs

Microsoft is an equal opportunity employer. Consistent with applicable law, all qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance and/or a reasonable accommodation due to a disability during the application process, read more about requesting accommodations ( .